1. Field
Exemplary embodiments of the present invention relate to a counting circuit, a delay value quantization circuit, and a latency control circuit.
2. Description of the Related Art
The integrated circuit has continuously improved the operation speed as well as the integration degree thereof. To improve the operation speed, a synchronous integrated circuit has emerged, which operates in synchronization with a clock signal applied from inside or generated from outside. Most operations of the synchronous integrated circuit are performed in synchronization with a clock signal. With the increase in the operation speed of the integrated circuit and the frequency of the clock signal used in the integrated circuit, securing a margin for a correct operation of the integrated circuit has become an important issue.
Meanwhile, the synchronous integrated circuit may perform a necessary operation by using information obtained by counting a clock signal. Hereafter, a case in which the integrated circuit uses information obtained by counting a clock signal during a data read operation of a memory will be taken as an example for description. When a read command is applied during a data read operation, the memory outputs data to the outside at a time point when a time that corresponds to a latency value passes from a time point when the read command is applied.
The reason why the memory does not immediately output data at the time point when the read command is applied, but outputs data to the outside at the time point when the time that corresponds to the latency value passes is that the memory requires a time for calling data stored therein and preparing output. For a mutual operation between integrated circuits A and B, a predetermined waiting time is required until the integrated circuit A requests the integrated circuit B to perform a certain operation, and the integrated circuit B performs the operation in response to the request. Such a waiting time refers to latency. For example, when CAS latency (CL) is set to seven, a memory transfers data to a memory controller after seven clocks from a time point when a read command is applied. Here, a circuit for controlling latency refers to a latency control circuit.
During the read operation of the memory, data, which are outputted to a memory cell in response to a read command, are stored in a pipe latch included in a data output circuit of the memory, and then outputted to the outside of the memory in response to a signal for deciding an output time point of the data (hereafter, referred to as an output signal). Such an output signal is activated at a time point when a time that corresponds to a latency value passes from a time point when the read command is applied, and generated by delaying the read command (or a signal activated in response to the read command). The latency control circuit delays the read command to generate the output signal. At this time, the read command not only may be delayed by the latency control circuit, but also may be delayed by internal components of the integrated circuit, positioned before and after the latency control circuit (hereafter, the delay value is referred to as a path delay value). When the latency control circuit delays the read command by the latency value, the output signal may be activated at a time point when the latency value and the path delay value pass from the time point when the read command is applied.
Therefore, the latency control circuit delays the read command by a difference between the latency value and the path delay value, instead of the latency value. At this time, the latency value is applied based on the clock signal, but the path delay value is not applied based on the clock signal. Therefore, the latency control circuit generates path information by quantizing the path delay value based on the clock signal for the above-described operation, and then performs an operation on the latency value and the path information to acquire a delay value by which the latency control circuit must actually delay the read command (based on the clock signal). Here, the path information may be generated by using a result outputted by counting the clock signal during the path delay value. The latency control circuit generates and stores the path information when the memory is powered on. Then, when a read command is applied, the latency control circuit delays and outputs the read command in consideration of the stored path information.
FIG. 1A is a configuration diagram of a conventional path information generation circuit.
Referring to FIG. 1A, the conventional path information generation circuit includes a delay unit 110 and a counting unit 120. The delay unit 110 is configured to delay a start signal ST by a path delay value, and the counting unit 120 is configured to count a clock signal CLK until an output of the delay unit 110 is activated from a time point when the start signal ST is activated.
When the start signal ST is activated, the counting unit 120 starts to count the clock signal CLK. When the start signal ST is delayed by the delay unit 110, the output of the delay unit 110 is activated. Then, when the output of the delay unit 110 is activated, the counting unit 120 ends counting the clock signal CLK. Here, because the delay value of the delay unit is equal to the path delay value, a difference between a time point when the start signal ST is activated and a time point when the output of the delay unit 110 is activated corresponds to the path delay value, and the counting unit 120 outputs a result K<0:A> that is obtained by counting the clock signal CLK by the path delay value.
FIG. 1B is a timing diagram that illustrates and explains the operation of the circuit of FIG. 1A.
The counting unit 120 starts to count the clock signal CLK from a time point T1 when the start signal ST is activated, and counts the clock signal CLK to a time point T2 when an output DEL_ST of the delay unit is activated. Here, a time between ‘T1’ and ‘T2’ corresponds to a path delay value CD. The output K<0:A> of the counting unit 120 may be obtained by quantizing the path delay value CD based on the clock signal CLK.
Here, a period M between rising edges R1 and R2 of the clock signal CLK, which are positioned before and after the time point T2 when the output DEL_ST of the delay unit is activated, becomes a margin for correctly counting the clock signal CLK during the path delay value CD. However, as the frequency of the clock signal CLK increases, such a margin may decrease to cause noise. In this case, the value obtained by counting the clock signal CLK during the path delay value CD may not be outputted correctly.